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Title: A 12-Bit Reference Error Calibrated SAR ADC
Department: Department of Electrical and Computer Engineering
Faculty: Faculty of Science and Technology
Issue Date: 2015
Citation: LIO, C. L., & HO, I. M., & ZHANG, W. H. (2015). A 12-Bit Reference Error Calibrated SAR ADC (Outstanding Academic Papers by Students (OAPS)). Retrieved from University of Macau, Outstanding Academic Papers by Students Repository.
Abstract: Analog-to-digital converter (ADC) functions as a bridge between the analog and digital worlds. It has wide applications such as cell phones, cameras and high-definition televisions. Due to the development of CMOS technology downscaling, the channel length and the supply voltage of the device shrink significantly, hence the digital circuit, which is less sensitive to noise, benefits in the aspects of speed and power consumption. Successive-approximation-register (SAR) ADC becomes popular recently thanks to its digital assisted nature. It consists of capacitive digital-to-analog converter (DAC), dynamic comparator and SAR logic. The conversion of the SAR ADC relies on the DAC to perform the binary searched feedback between the input signal and the reference voltage, while for high-speed design the DAC settling time becomes the major limitation in speed and accuracy. Moreover, the package inductive bonding generating switching noise due to current transient of the DAC causes reference voltage variations that further degrade the conversion accuracy. This project presents a 12-bit 130-MS/s reference calibrated SAR ADC in 65-nm CMOS using proposed dynamic capacitive-error-compensation (DCEC) technique to suppress the DAC settling and the reference errors in the most-significant-bits (MSBs) transitions. These signal-dependent errors are estimated and compensated in analog domain. The solution costs less implementation effort and does not sacrifice the dynamic range of the conversion. In addition, the comparisons between the proposed method and the existing solutions are analyzed in detail and the corresponding mathematical model in MATLAB is provided. The DCEC scheme was implemented in a 130-MS/s 12-bit SAR ADC with only 3-pF reference decoupling capacitance. The post-layout simulation result shows that the proposed solution can effectively improve the SNDR from 52 dB to 65 dB with only 4 mW power dissipation, achieving the Figure-of-Merit (FoM) of 21 fJ/conv.step.
Instructor: Prof. U, SENG PAN, Prof. ZHU, YAN
Programme: Bachelor of Science in Electrical and Computer Engineering
Appears in Collections:FST OAPS 2015

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